1～3 item / All 3 items
Sprite Drawing IP Core (Verilog)
This process overlays character images (sprites) onto a background image. The maximum image size is 1024x1024. Arbitrary angle rotation in 0.35-degree increments. During rotation, a bi-linear interpolated image is created. Mirror flipping. Alpha blending. The maximum number of overlays is 16.
Enlarge/Reduce IP Core (Verilog)
P1_Scale performs image scaling using multi-rate signal processing in hardware. The maximum image size is 1024x1024, and the scaling ratio is N/M where N and M can be 1, 2, 3, 4, 5, 6, 7, or 8.
JPEG compression IP core (Verilog)
Verilog-HDL JPEG compression IP core Compression method: JPEG Base Line method Input format: RGB 8:8:8 Output format: YUV 4:2:0 4:2:2 4:4:4 Huffman coding: Standard settings (Annex K) used Can also be set in registers Quantization table: Standard settings (Annex K) used Can also be set in registers
